In the fabrication of semiconductor integrated circuits (ICs), active device regions are formed in semiconductor substrates, isolated from adjacent devices. Specific electrical paths connect such active devices, using high-conductivity, thin-film structures. Such structures make contacts with active devices through openings, or contact holes, in the isolating material. Of primary concern is the formation of low-resistivity contacts, in order to ensure devices perform properly. As ICs are scaled down in size, so are the devices which make up the ICs. Increases in resistance are associated with increasing circuit density and adversely affect device performance. Ways to decrease the overall resistance of ICs, including contacts, are crucial to continued successful device performance.
One way in which circuit resistance is decreased is by creating low-resistance, ohmic contacts at the device level. Ohmic contacts exhibit nearly linear current-voltage characteristics in both directions of current flow. Various factors affect the type of contact which is maintained. Increasing dopant concentration in the semiconductor contact area decreases contact resistance, up to the solubility of the dopant at the temperature at which it is introduced. Unclean semiconductor surfaces (i.e., those which contain a native oxide film) increase contact resistance. Native oxides are a problem due to silicon's rapid oxidation rate when exposed to an oxygen ambient. The most widely used method for removal of such oxides is by dipping the wafer in a hydrofluoric acid solution. However, this does not provide perfect cleaning of the semiconductor substrate because some native oxide forms between the time of the hydrofluoric acid dip and the deposition of metal contacts. Sputter etching has been used in an attempt to alleviate this imperfection, but it falls short because more oxide is introduced onto the semiconductor substrate than is removed.
Conventional process steps for formation of ohmic contacts to semiconductor substrates include the following: formation of heavily doped regions where contacts are to be made, etching a contact hole in the isolating oxide layer which covers the semiconductor substrate, cleaning the semiconductor surface to remove native oxide, depositing a metal film over the wafer by physical vapor deposition (PVD), and annealing to improve the metal-to-semiconductor contact. During the metal deposition step, obtaining good bottom step coverage is very important in maintaining the overall ohmic contact. High-aspect ratio (ratio of height-to-opening of a contact hole) holes make it even more difficult to achieve good bottom step coverage. Such holes are much deeper than they are wide, preventing good bottom step coverage by the conventional process steps.
The type of film deposition has an effect on the resulting step coverage. Chemical vapor deposition (CVD) processes are more likely to fill high-aspect ratio holes than physical vapor deposition (PVD) processes. However, some films cannot be deposited using CVD, due to contamination introduced by CVD processes. CVD is often accompanied by a significant amount of carbon, chlorine, oxygen, and other contaminants that are detrimental to device performance. Forming films that are free from contamination is even more important as devices decrease in size. Defects resulting from such contamination are even more dominant in thinner films, which are present in smaller devices.
Different types of metal layers are used to improve ohmic contacts. The most commonly used metals are reacted with underlying silicon to form silicides. Titanium silicide is the most commonly used metal silicide due to its superior qualities, one being its ability to getter oxygen. Titanium silicide forms good ohmic contacts with both polysilicon and single-crystal silicon doped contact areas. Silicides, in general, are preferred for contact formation due to their ability to reduce native oxide remaining on semiconductor substrates. This reduction occurs because titanium reacts with native oxide to form titanium oxide and titanium silicide. The oxide layer remains on top of the silicide layer after annealing, separated from the underlying silicon.
As an effect of shrinking IC devices, device source/drain junction depths become shallower. When metals are deposited and then annealed to form a silicide, silicon is consumed from the shallow source/drain regions, to react with the metal to form a silicide. When shallow source/drain regions are depleted of silicon, they are more prone to junction leakage. Thus, consumption of silicon during annealing to form silicide must be as small as possible to prevent junction leakage. In general, for a particular thickness of deposited metal, a proportional thickness of silicon substrate is consumed, depending on the stoichiometry of the silicide formed. In particular, for a given thickness of deposited titanium, the amount of silicon consumed is approximately two times as thick, to form titanium silicide (TiSi.sub.2).
A primary method for depositing films by PVD is sputtering. Sputtering is a method by which atoms on a target are displaced to a desired surface, where they form a thin film. One possible solution to the problem of over consumption of silicon in shallow junctions is to use a PVD process to deposit a metal/silicon alloy, like titanium silicide. When the deposited material is an alloy, the target is generally a composite target consisting of two or more materials mechanically arranged in a selected ratio, to yield a film of the desired alloy composition.
One of the major problems associated with obtaining good bottom step coverage utilizing PVD is material "overhang" at the "shoulder" (i.e., the corner of a sidewall and the top surface) of contact openings. This is a result of imperfect lines of incidence traveled by sputtered target atoms, because, in general, sputtered atoms travel following the law of cosines. Doming of the sputtered material commonly occurs in the bottom of the contact hole due to material overhang. This results in poor bottom comer step coverage, which often leads to contact failure.
Even with the use of collimated sputtering, techniques of collimating the sputtering beam are not perfect to enable precision in angles of incidence on a substrate. Thus, excess sputtered metal forms at the top of the opening, such that the geometry of the metallized opening does not generally match the geometry of the underlying opening in the substrate.
There is a need to maintain adequate alloy bottom step coverage of contact holes and to decrease contact area resistance to prevent device failure. There is a further need to control the composition of such alloys, without significant consumption of silicon from the bottom of the contact hole.